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Data Sheet February 2003
LCK4973 Low-Voltage PLL Clock Driver
Features
s s s
Description
Agere Systems' LCK4973 is a 3.3 V/2.5 V, PLL-based clock driver for high-performance RISC or CISC processor-based systems. The LCK4973 has output frequencies of up to 240 MHz and skews of less than 250 ps, making it ideal for synchronous systems. The LCK4973 contains 12 low-skew outputs and a feedback/sync output for flexibility and simple implementation. There is a robust level of frequency programmability between the 12 low-skew outputs in addition to the input/output relationships. This allows for very flexible programming of the input reference versus the output frequency. The LCK4973 contains a flexible output enable and disable scheme. This helps execute system debug as well as offer multiple powerdown schemes, which meet green-class machine requirements. The LCK4973 features a power-on reset function, which automatically resets the device on powerup, providing automatic synchronization between QFB and other outputs. The LCK4973 is 3.3 V/2.5 V compatible and requires no external loop filters. It has the capability of driving 50 transmission lines. Series terminated lines have the ability of driving two 50 lines in parallel, effectively doubling the fanout.
Fully integrated PLL. Output frequency up to 240 MHz. Compatible with PowerPC (R) and Pentium (R) microprocessors. 52-pin TQFPT. 3.3 V/2.5 V power supply. Pin compatible with 973 type devices. 100 ps typical cycle-to-cycle jitter. Output skews of less than 250 ps.
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LCK4973 Low-Voltage PLL Clock Driver
Data Sheet February 2003
Pin Information
Pin Diagram
VCO_Sel
fsela0
fsela1
fselb0 41
52 VSS MROEB Frz_Clk Frz_Data fselFB2 PLL_EN Ref_Sel TCLK_Sel TCLK0 TCLK1 PCLK PCLK VDDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Inv_Clk
51
50
49
48
47
46
45
44
43
42
40 39 38 37 36 35 34 VSS Qb0 VDDO Qb1 VSS Qb2 VDDO Qb3 Ext_FB VSS QFB VDDI fselFB0
LCK4973
15 VSS
16 Qc3
17 VDDO
18 Qc2
19 fselc1
20 fselc0
21 Qc1
22 VDDO
23 Qc0
24 VSS
25 QSync
26 fselFB1
fselb1 33 32 31 30 29 28 27
VDDO
VDDO
Qa0
Qa1
Qa2
Qa3
VSS
VSS
2331.a (F)
Note: All inputs have internal pull-up resistors (50 k) except for PCLK and PCLK.
Figure 1. 52-Pin TQFPT
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Agere Systems Inc.
Data Sheet February 2003
LCK4973 Low-Voltage PLL Clock Driver
Pin Information (continued)
Pin Descriptions
Table 1. Pin Descriptions Pin 1, 15, 24, 30, 35, 39, 47, 51 2 Symbol VSS Type Ground I/O -- Ground. Description
MROEB
LVTTL
I
Master Reset and Output Enable Input. Note: When MR/OE is set high, the PLL will have been disturbed and the outputs will be at an indeterminate frequency until MR/OE is relocked.
3 4 5
Frz_Clk Frz_Data fselFB2
LVTTL LVTTL LVTTL
I I I
Freeze Mode. Freeze Mode. Feedback Output Divider Function Select. This input, along with pins fselFB0 and fselFB1, controls the divider function of the feedback bank of outputs. See Table 3 for more details. PLL Bypass Select. 0 = The internal PLL is bypassed and the selected reference input provides the clocks to operate the device. 1 = The internal PLL provides the internal clocks to operate the device. Reference Select Input. The Ref_Sel input controls the reference input to the PLL. 0 = The input is selected by the TCLK_Sel input. 1 = The PCLK is selected. TTL Clock Select Input. The TCLK_Sel input controls which TCLK input will be used as the reference input if Ref_Sel is set to 0. 0 = TCLK0 is selected. 1 = TCLK1 is selected. LVTLL Reference Input. These inputs provide the reference frequency for the internal PLL when selected by Ref_Sel and TCLK_Sel. Differential Reference Input. This low-voltage differential PECL input provides the reference frequency for the internal PLL when selected by Ref_Sel. Differential Reference Input. This low-voltage differential PECL input provides the reference frequency for the internal PLL when selected by Ref_Sel. Invert Mode. This input only affects the Qc bank. 0 = All outputs of the Qc bank are in the normal phase alignment. 1 = Qc2 and Qc3 are inverted from the normal phase of Qc0 and Qc1. Clock Output. These outputs, along with the Qa[0:3], Qb[0:3], and QFB outputs, provide numerous divide functions determined by the fsela[0:3], fselb[0:3], and the fselFB[0:2] See Table 2 and Table 3 for more details.
6
PLL_EN
LVTTL
I
7
Ref_Sel
LVTTL
I
8
TCLK_Sel
LVTTL
I
9, 10 11
TCLK[0:1] PCLK
LVTTL LVTTL
I I
12
PCLK
LVTTL
I
13 14
VDDA Inv_Clk
Power LVTTL
-- PLL Power. I
16, 18, 21, 23 17, 22, 33, 37, 45, 49
Qc[3:0]
LVTTL
O
VDDO
Power
-- Output Buffer Power.
Agere Systems Inc.
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LCK4973 Low-Voltage PLL Clock Driver
Data Sheet February 2003
Pin Information (continued)
Pin Descriptions (continued)
Table 1. Pin Descriptions (continued) Pin 19, 20 25 Symbol fselc[1:0] QSync Type LVTTL LVTTL I/O I O Description Output Divider Function Select. Each pair controls the divider function of the respective bank of outputs. See Table 2 for more details. PLL Lock Indicator. 0 = The PLL is attempting to acquire lock. 1 = This output indicates that the internal PLL is locked to the reference signal. Note: If there is no activity on the selected reference input, QSync may not accurately reflect the state of the internal PLL. This pin will drive logic, but not Thevenin terminated transmission lines. It is always active and does not go to a high-impedance state. QSync provides TEST MODE information when PLL_EN is set to 0. 26 fselFB1 LVTTL I Feedback Output Divider Function Select. This input, along with pins fselFB1 and fselFB2, controls the divider function of the feedback bank of outputs. See Table 3 for more details. Feedback Output Divider Function Select. This input, along with pins fselFB0 and fselFB2, controls the divider function of the feedback bank of outputs. See Table 3 for more details. Clock Output. This output, along with the Qa[0:3] and Qc[0:3] outputs, provides numerous divide functions determined by the fsela[0:3], fselb[0:3], and the fselFB[0:2]. See Table 2 and Table 3 for more details. PLL Feedback Input. This input is used to connect one of the clock outputs (usually QFB) to the feedback input of the PLL. Clock Output. These outputs, along with the Qa[0:3], Qc[0:3], and QFB outputs, provide numerous divide functions determined by the fsela[0:3], fselb[0:3], and the fselFB[0:2]. See Table 2 and Table 3 for more details. Output Divider Function Select. Each pair controls the divider function of the respective bank of outputs. See Table 2 for more details. Output Divider Function Select. Each pair controls the divider function of the respective bank of outputs. See Table 2 for more details. Clock Output. These outputs, along with the Qb[0:3], Qc[0:3], and QFB outputs, provide numerous divide functions determined by the fsela[0:3], fselb[0:3], and the fselFB[0:2]. See Table 2 and Table 3 for more details. VCO Frequency Select Input. This input selects the nominal operating range of the VCO used in the PLL. 0 = The VCO range is 100 MHz--240 MHz. 1 = The VCO range is 200 MHz--480 MHz.
27
fselFB0
LVTTL
I
28 29
VDDI QFB
Power LVTTL
-- PLL Power. O
31 32, 34, 36, 38 40, 41 42, 43 44, 46, 48, 50 52
Ext_FB Qb[3:0]
LVTTL LVTTL
I O
fselb[1:0] fsela[1:0] Qa[3:0]
LVTTL LVTTL LVTTL
I I O
VCO_Sel
LVTTL
I
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Agere Systems Inc.
Data Sheet February 2003
LCK4973 Low-Voltage PLL Clock Driver
Table 2. Function Table for Qa, Qb, and Qc
fsela1 fsela0 Qa fselb1 fselb0 Qb fselc1 fselc0 Qc 0 0 1 1 0 1 0 1 /4 /6 /8 /12 0 0 1 1 0 1 0 1 /4 /6 /8 /10 0 0 1 1 0 1 0 1 /2 /4 /6 /8
Functional Description
Using the select lines (fsela[1:0], fselb[1:0], fselc[1:0], fselFB[2:0]), the following output frequency ratios between outputs can be obtained:
s s s s s s s s s s s
1:1 2:1 3:1 3:2 4:1 4:3 5:1 5:2 5:3 6:1 6:5
Table 3. Function Table for QFB fselFB21 0 0 0 0 1 1 1 1 fselFB1 0 0 1 1 0 0 1 1 fselFB0 0 1 0 1 0 1 0 1 QFB /4 /6 /8 /10 /8 /12 /16 /20
This can be achieved by pushing low the control signal one clock edge before the coincident edges of outputs Qa and Qc. The synchronization output indicates when these rising edges will occur. Selectability of feedback frequency is independent on the output frequencies. Output frequencies can be odd or even multiples of the input reference clock, as well as being less than the input frequency. The power-on reset function is designed to reset the system after powerup for synchronization between QFB and other outputs. This solves the problem of resetting if fselFB2 is held high on powerup. All other conditions of the fsel pins automatically synchronize during PLL clock acquisition. All outputs are initialized active on power on. The LCK4973 independently enables each output through a serial input port. When disabled (frozen), the outputs will lock in the low state, but internal state machines are unaffected. When re-enabled, the outputs initialize in phase and synchronous with those not reactivating. This freezing only happens when the outputs are in the low state, preventing runt pulse generation.
1. If fselFB2 is set to 1, it may be necessary to apply a reset pulse after powerup in order to ensure synchronization between the QFB and other inputs.
Table 4. Function Table for Logic Selection Control Pin VCO_Sel Ref_Sel TCLK_Sel PLL_EN MR/OE Inv_Clk Logic 0 VCO/2 TCLK TCLK0 Bypass PLL Master Reset/ Output High-Z Noninverted Qc2, Qc3 Logic 1 VCO Xtal (PECL) TCLK1 Enable PLL Enable Outputs Inverted Qc2, Qc3
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LCK4973 Low-Voltage PLL Clock Driver
Data Sheet February 2003
Functional Description (continued)
PCLK PCLK
VCO_Sel PLL_EN REF_Sel
TCLK0 TCLK1 TCLK_Sel Ext_FB
0 1
0 PHASE DETECTOR LPF VCO 1
DQ
SYNC Frz
Qa0 Qa1 Qa2 Qa3
DQ
SYNC Frz
Qb0 Qb1 Qb2 Qb3
fselFB2
MR/OE POWER-ON RESET /4, /6, /8, /12 /4, /6, /8, /10 /2, /4, /6, /8 fsela0:1 fselb0:1 fselc0:1 fselFB0:1 2 2 2 2 /4, /6, /8, /10 SYNC PULSE DATA GENERATOR /2 0 1
DQ SYNC Frz DQ SYNC Frz
Qc0 Qc1 Qc2 Qc3 QFB
DQ
DQ
SYNC Frz
QSync
Frz_Clk OUTPUT DISABLE CIRCUITRY Frz_Data Inv_Clk 2332.a (F) 12
Figure 2. LCK4973 Logic Diagram
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Agere Systems Inc.
Data Sheet February 2003
LCK4973 Low-Voltage PLL Clock Driver
asserted to half the frequency if the needed feedback frequency is half of the lowest frequency output. This multiplies the output frequencies by a factor of two, relative to the input reference frequency. Assume the previously mentioned 5:3:2 ratio, with the highest output frequency of 100 MHz. If the only available reference frequency is 50 MHz, the setup of Figure 3 can be used. The device provides 100 MHz, 66 MHz, and 40 MHz outputs, all generated from the 50 MHz source. Figure 4 and Figure 5 also show possible configurations of the LCK4973.
Functional Description (continued)
Device Programming
The LCK4973 contains three independent banks of four outputs as well as an independent PLL feedback output. The possible configurations make Agere Systems' LCK4973 one of the most versatile frequency programming devices. Table 5 shows various selection possibilities. Table 5. Programmable Output Frequency Relationships for Qa, Qb, and Qc (VCO_Sel = 1) fselb1 fselb0 fsela1 fsela0 fselc1 Qa VCO/4 VCO/6 VCO/8 VCO/12 Qb VCO/4 VCO/6 VCO/8 VCO/10 fselc0 Qc VCO/2 VCO/4 VCO/6 VCO/8
0 0 1 1
0 1 0 1
0 0 1 1
0 1 0 1
0 0 1 1
0 1 0 1
0 0 1 1 0 1 0 1 0
LCK4973 fsela0 fsela1 fselb0 fselb1 fselc0 fselc1 fselFB0 fselFB1 fselFB2
Qa Qb Qc QFB
4 4 4
100 MHz 40 MHz 66.66 MHz 50 MHz
Table 6. Programmable Output Frequency Relationships for QFB (VCO_Sel = 1) fselFB2 0 0 0 0 1 1 1 1 fselFB1 0 0 1 1 0 0 1 1 fselFB0 0 1 0 1 0 1 0 1 QFB VCO/4 VCO/6 VCO/8 VCO/10 VCO/8 VCO/12 VCO/16 VCO/20
50 MHz
Input Ref Ext_FB
VCO = 400 MHz
2334.a (F)
Figure 3. 100 MHz from 50 MHz Example
To determine the relationship between the three banks, one would compare their divide ratios. For example, if one desired a ratio of 5:3:2, set Qa to /10, Qb to /6, and Qc to /4. These selections would yield a 5:3:2 ratio. For low frequency circumstances, the VCO_Sel pin allows the option of an additional /2 to be added to the clock path. This pin maintains the output relationships, but provides an extended clock range for the PLL. The feedback output is matched to the input reference frequency after the output frequency relationship is set and VCO is in a stable range. Only an external feedback is provided to the PLL in the LCK4973 device to optimize flexibility. If, in the previous example, the input reference frequency were equal to the lowest output frequency, the output would be set to /10 mode. The fselFB2 input could be Agere Systems Inc.
0 0 0 0 1 1 1 1 0
LCK4973 fsela0 fsela1 fselb0 fselb1 fselc0 fselc1 fselFB0 fselFB1 fselFB2
Qa Qb Qc QFB
4 4 4
60 MHz (PROCESSOR) 60 MHz (PROCESSOR) 30 MHz (PCI) 24 MHz (FLOPPY DISK CLK)
24 MHz
Input Ref Ext_FB
2335.a (F)
Figure 4. Pentium Compatible Clocks Example
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LCK4973 Low-Voltage PLL Clock Driver
Data Sheet February 2003
It is most likely that the LCK4973 will be used as a zero-delay buffer in a nested clock-tree application. In these instances, the LCK4973 offers a LVPECL clock input as the PLL reference. This allows the user to utilize the exceptional skew performance of the device as the primary clock distribution device. The device can then lock onto the LVPECL reference and translate, with near-zero delay, to low-skew LVCMOS outputs. These clock trees will show tighter skews than CMOS fanout buffer clock trees.
Functional Description (continued)
Device Programming (continued)
LCK4973 fsela0 fsela1 fselb0 fselb1 fselc0 fselc1 fselFB0 fselFB1 fselFB2
1 1 0 1 1 1 1 1 1
Qa Qb Qc QFB
4 4 4
33 MHz (PCI) 50 MHz (PROCESSOR) 50 MHz (PROCESSOR) 20 MHz (ETHERNET)
SYNC Output
When the output frequencies are not integer multiples of each other, there is a need for a signal for synchronization purposes. The SYNC output is designed to address this need. The Qa and Qc banks of outputs are monitored by the device, and a lowgoing pulse (one period in duration, on period before the coincident rising edges of Qa and Qc) is provided. The duration and placement of the pulse is dependent on the highest of Qa and Qc output frequencies. The timing diagram, (Figure 8 on page 10) show the various waveforms for SYNC. Note: SYNC is defined for all possible combinations of Qa and Qc, even though the lower frequency clock should be used as a synchronizing signal in most cases.
20 MHz
Input Ref Ext_FB
2336.a (F)
Figure 5. 20 MHz Source Example The Lnv_Clk input pin, when asserted, will invert the Qc2 and Qc3 outputs.This inversion does not affect the output-output skew of the device and allows for the development of 180 phase-shifted clocks. This output can also be used as a feedback output or routed to a second PLL to generate early/late clocks. Figure 5 on page 8 shows a 180 phase-shift configuration.
Zero-Delay Buffer Use
The LCK4973 can be used as a zero-delay buffer due to the external feedback of the device. Using one of the inputs as a feedback to the PLL eliminates the propagation delay through the device. A near-zero delay is produced by the PLL aligning to the output edge to the input reference edge. The static phase offset and the relative delay between the inputs and outputs are affected by the reference frequency. This is because the static phase offset is a function of the reference clock and Tpd of the LCK4973 is a function of the configuration used.
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Agere Systems Inc.
Data Sheet February 2003
LCK4973 Low-Voltage PLL Clock Driver
Functional Description (continued)
SYNC Output (continued)
0 0 0 0 1 0 0 0 0 1
LCK4973 fsela0 fsela1 fselb0 fselb1 fselc0 fselc1 fselFB0 fselFB1 fselFB2 Inv_Clk
Qa Qb Qc Qc QFB
4 4 2 2
66 MHz 66 MHz 66 MHz 66 MHz
0 1 0 1 1 1 0 0 0 0
LCK4973 fsela0 fsela1 fselb0 fselb1 fselc0 fselc1 fselFB0 fselFB1 fselFB2 Inv_Clk
Qa Qb Qc QFB
4 4 4
33 MHz SHIFTED 90 33 MHz SHIFTED 90 33 MHz SHIFTED 90 66 MHz 66 MHz 66 MHz 33 MHz SHIFTED 90
2337.a (F)
66 MHz
Input Ref Ext_FB
Input Ref Ext_FB
Figure 6. Phase Delay Example Using Two LCK4973s
100 75 50 25 ps 0 -25 -50 -75 -100 Qc3 Qc2 Qc1 Qc0 Qb3 Qb2 Qb1 Qb0 Qa3 Qa2 Qa1 Qa0 QFB
2338.a (F) r.1
Figure 7. Typical Skews Relative to QA
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LCK4973 Low-Voltage PLL Clock Driver
Data Sheet February 2003
Functional Description (continued)
SYNC Output (continued)
fVCO 1:1 MODE Qa Qc Sync 2:1 MODE Qa Qc Sync 3:1 MODE Qc(/2) Qa(/6) Sync 3:2 MODE Qa(/4) Qc(/6) Sync 4:1 MODE Qc(/2) Qa(/8) Sync 4:3 MODE Qa(/6) Qc(/8) Sync 6:1 MODE Qa(/12) Qc(/2) Sync
2333.a (F)
Figure 8. LCK4973 Timing
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Agere Systems Inc.
Data Sheet February 2003
LCK4973 Low-Voltage PLL Clock Driver
used in a point-to-point scheme. The parallel configuration terminates the signal at the end of the line with a 50 resistance to VDD/2. Only one terminated line can be driven by each output of the LCK4973 due to the high level of dc current drawn. In a series-terminated case, there is no dc current draw, and the outputs can drive multiple series-terminated lines. Figure 10 shows these scenarios.
Functional Description (continued)
Power Supply Filtering
The LCK4973 is a mixed-signal product which is susceptible to random noise, especially when this noise is on the power supply pins. To isolate the output buffer switching from the internal phase-locked loop, the LCK4973 provides separate power supplies for the internal PLL (VDDA) and for the output buffers (VDDO). In a digital system environment, besides this isolation technique, it is highly recommended that both VDDA and VDD power supplies be filtered to reduce the random noise as much as possible. Figure 9 illustrates a typical power supply filter scheme. Due to its susceptibility to noise with spectral content in this range, a filter for the LCK4973 should be designed to target noise in the 100 kHz to 10 MHz range. The RC filter in Figure 9 will provide a broadband filter with approximately 100:1 attenuation for noise with spectral content above 20 kHz. More elaborate power supply schemes may be used to achieve increased power supply noise filtering.
LCK4973 OUTPUT BUFFER 7 RS = 43 ZO = 50 OUTA
IN
LCK4973 OUTPUT BUFFER 7
RS = 43
ZO = 50 OUTB0
IN
ZO = 50 RS = 43 OUTB1
3.3 V
2340.a (F)
Figure 10. Dual Transmission Lines
RS = 5 --10
VDDA 0.01 F
LCK4973
22 F
VDD 0.01 F
2344.a (F)
The waveform plots of Figure 11 show the simulated results of a single output versus a two-line output. A 43 ps delta exists between the two differently loaded outputs that can be seen in Figure 11. This implies that dual-line driving need not be used in order to maintain tight output-to-output skew. The step in Figure 11 shows an impedance mismatch caused when looking into the driver. The parallel combination in Figure 10 plus the output resistance does not equal the parallel combination of the line impedances. The voltage wave down the lines will equal the following: VL = VS (Z0/RS + R0 + Z0) = 3.0 (25/53.5) = 1.4 V The voltage will double at the load-end to 2.8 V, due to the near-unity reflection coefficient. It then continues to increment towards 3.0 V in one-round trip delay steps (4 ps). This step will not cause any false clock triggering, but some may not want these reflections on the line. Figure 12 shows a possible configuration in order to eliminate these reflections. In this scenario, the series terminating resistors are reduced so the line impedance is matched when the parallel combination is added to the output buffer.
Figure 9. Power Supply Filter
Driving Transmission Lines
The output drivers of the LCK4973 were designed for the lowest impedance possible for maximum flexibility. The LCK4973's 10 impedance, the drivers can accommodate either parallel or series terminated transmission lines. Point-to-point distribution of signals is the preferred method in today's high-performance clock networks. Series-terminated or parallel-terminated lines can be Agere Systems Inc.
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LCK4973 Low-Voltage PLL Clock Driver
Data Sheet February 2003
The freeze mechanism allows serial loading of the 12-bit serial input register. this register contains one programmable freeze enable bit for 12 of the 14 output clocks. The Qc0 and QFB outputs cannot be frozen with the serial port, which prevents possible lock-up situations if there is an error in the serial input register. The user can also program a freeze by writing 0 to the respective freeze bit. Likewise, it can be programmability unfrozen by writing a 1 to that same bit. Freeze logic cannot force a recently frozen clock to a logic 0 state before the time which it would normally transition to that state. The logic will only maintain the frozen clock in logic 0. Similarly, the logic will not force a recently frozen clock to logic 1 before the time it would normally transition there. when the clock would normally be in a logic 0 state, the logic re-enables the unfrozen clock, eliminating the possibility of runt clock pulses.
Functional Description (continued)
Driving Transmission Lines (continued)
3.0 OUTA tD = 3.8956 OUTB tD = 3.9386
2.5
VOLTAGE (V)
2.0 IN 1.5
1.0
0.5
0 2 4 6 8 TIME (ns) 10 12 14
2341.a (F)
Figure 11. Single vs. Dual Waveforms
The user may write to the serial input register by supplying a logic 0 start bit followed (serially) by 12 NRZ freeze bits through Frz_Data. The period of the Frz_Clk signal equals the period of each Frz_Data bit. The timing should be such that the LCK4973 is able to sample each Frz_Data bit with the rising edge of the Frz_Clk (free-running) signal.
LCK4973 OUTPUT BUFFER 7
RS = 36
ZO = 50
START BIT D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
2343.a (F)
ZO = 50 RS = 36
Note: D0--D3: control bits for Qa0--Qa3, respectively. D4--D7: control bits for Qb0--Qb3, respectively. D8--D10: control bits for Qc1--Qc3, respectively. D11: control bit for QSync.
7 + 36 36 = 50 50 25 = 25
2342.a (F)
Figure 13. Freeze Data Input Protocol
Figure 12. Optimized Dual Transmission Lines
Output Freeze Circuitry
The new green classification for computers requires unique power management. The LCK4973's individual output enable control allows software to implement unique power management. A serial interface was created to eliminate individual output control at the cost of one pin per output. The freeze control logic provides a mechanism for the LCK4973's clock inputs to be stopped in the logic 0 state.
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Agere Systems Inc.
Data Sheet February 2003
LCK4973 Low-Voltage PLL Clock Driver
Absolute Maximum Ratings
Stresses which exceed the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods of time can adversely affect device reliability. Table 7. Absolute Maximum Ratings Parameter Supply Voltage Input Voltage Input Current Storage Temperature Range Symbol VDD VI IIN Tstg Min -0.3 -0.3 -- -40 Max 4.6 VDD + 0.3 20 125 Unit V V mA C
Electrical Characteristics
Table 8. PLL Input Reference Characteristics (TA = -40 C to 85 C) Parameter TCLK Input Rise/Fall Reference Input Frequency Reference Input Duty Cycle Symbol tr, tf fref trefDC Condition -- -- -- Min -- --1 25 Max 3.0 --1 75 Unit ns MHz %
1. Maximum input reference frequency is limited by VCO lock range and the feedback driver or 100 MHz. Minimum input reference frequency is limited by the VCO lock range and the feedback divider.
dc Characteristics
Table 9. dc Characteristics (TA = -40 C to 85 C, VDD = 3.3 V 5%) Parameter Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Current Maximum Supply Current Analog VDD Current Input Capacitance Power Dissipation Capacitance Symbol VIH VIL VOH VOL IIN IDD IDDA CIN Cpd Condition -- -- IOH = -20 mA1 IOL = 20 mA1 --2 All VDD pins VDDA pin only3 -- Per output Min 2.0 -- 2.4 -- -- -- -- -- -- Typ -- -- -- -- -- 130 60 -- 25 Max 3.6 0.8 -- 0.5 Unit V V V V A mA mA pF pF
120
160 85 4 --
1. The LCK4973 inputs can drive series of parallel terminated transmission lines on the incident edge. 2. Inputs have pull-up/pull-down resistors which affect input current. 3. Qa = Qb = Qc = 50 MHz, unoladed outputs.
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LCK4973 Low-Voltage PLL Clock Driver
Data Sheet February 2003
Electrical Characteristics (continued)
dc Characteristics (continued)
Table 10. dc Characteristics (TA = -40 C to 85 C, VDD = 2.5 V 5%) Parameter PLL Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Current Analog VDD Current Maximum Supply Current Symbol VDD_PLL VIH VIL VOH VOL IIN IDDA IDD Condition LVCMOS LVCMOS LVCMOS IOH = -15 mA2 IOL = 15 mA VIN = VDD or GND VDDA Pin Only3 All VDD Pins Min 2.325 1.7 -0.3 1.8 -- -- -- -- Typ -- -- -- -- -- -- 60 130 Max VDD VDD + 0.3 0.7 -- 0.6 Unit V V V V V A mA mA
120
85 160
1. VCMR(dc) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the Vp-p(dc) specification. 2. The LCK4973 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. 3. Qa = Qb = Qc = 50 MHz, unoladed outputs.
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Agere Systems Inc.
Data Sheet February 2003
LCK4973 Low-Voltage PLL Clock Driver
Electrical Characteristics (continued)
ac Characteristics
Table 11. ac Characteristics (TA = -40 C to 85 C, VDD = 3.3 V/2.5 V 5%)1, 2 Parameter Symbol Condition PLL locked 50.0 33.3 25.0 20.0 16.6 12.5 8.33 6.25 -- 150 100.0 50.0 33.3 25.0 20.0 16.6 12.5 10.0 8.33 -- 25 -- -- -- -- 47 0.1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 150 150 -- 50 -- -- -- -- TBD TBD -- 10 120.0 80.0 60.0 48.0 40.0 30.0 20.0 15.0 TBD 500 240.0 120.0 80.0 60.0 48.0 40.0 30.0 24.0 20.0 20 75 1.0 -- -- 250 53 1.0 8 8 100 -- -- TBD -- Min Typ Max Unit MHz
fREF Input Reference Frequency: /4 feedback /6 feedback /8 feedback /10 feedback /12 feedback /16 feedback /24 feedback /32 feedback Input Reference Frequency in PLL Bypass Mode3 fREF 4 VCO Frequency Range fVCO fMAX Output Frequency: /2 feedback /4 feedback /6 feedback /8 feedback /10 feedback /12 feedback /16 feedback /20 feedback /24 feedback Serial Interface Clock Frequency fSTOP_CLK Reference Input Duty Cycle fREFDC CCLKx Input Rise/Fall Time tR, tF Propagation Delay (static phase offset) t() CCLKx to FB_IN PCLK to FB_IN Output-to-Output Skew tSK(O) Output Duty Cycle DC Output Rise/Fall Time tR, tF Output Disable Time tPLZ, HZ Output Enable Time tPZL, LZ Cycle-to-Cycle Jitter (RMS 1) tJIT(CC) Period Jitter (RMS 1) tJIT(PER) I/O Phase Jitter (RMS 1) tJIT() PLL Closed Loop Bandwidth BW Maximum PLL Lock Time tLOCK
PLL bypass -- PLL locked
MHz MHz MHz
-- -- 20% to 80% PLL locked
MHz % ns ps
-- -- 20% to 80% -- -- -- -- -- -- --
ps % ns ns ns ps ps ps kHz ms
1. All ac characteristics are design targets and subject to change upon device characterization. 2. ac characteristics apply for parallel output termination of 50 to VTT. 3. In bypass mode, the LCK4973 divides the input reference clock. 4. The input reference frequency must match the VCO lock range divided be the total feedback divider ratio: fREF = fVCO / (M x VCO_SEL). 5. VCMR(ac) is the crosspoint of the differential input signal. Normal ac operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the Vp-p(ac) or Vp-pVp-pVp-p impacts static phase offset t().
Agere Systems Inc.
15
LCK4973 Low-Voltage PLL Clock Driver
Data Sheet February 2003
Outline Diagram
52-pin TQFPT package outline. All dimensions are in millimeters.
12.00 10.00 PIN #1 IDENTIFIER ZONE
52 40
1.00 REF
1
39
0.25 GAGE PLANE SEATING PLANE 10.00 12.00 DETAIL A 0.45/0.75
13
27
14
26
DETAIL A
DETAIL B
0.09/0.20 1.00 0.05 0.22/0.38 1.20 MAX SEATING PLANE 0.08 DETAIL B 0.08
M
0.65 TYP
0.05/0.15
PowerPC is a registered trademark of International Business Machines Corporation. Pentium is a registered trademark of Intel Corporation.
For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 1344 296 400
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere, Agere Systems, and the Agere logo are trademarks of Agere Systems Inc.
Copyright (c) 2003 Agere Systems Inc. All Rights Reserved
February 2003 DS03-073LCK (Replaces DS03-015LCK)

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